AMD XDNA2 NPU Backend — Changelog Index

R

Research Survey — Independent NPU Performance Literature

21 sources · AIE utilisation spectrum · cross-vendor LLM comparison · kernel optimisation paths · 2026-03-30

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12

Phase 12 — Micro-Tile Optimization (128×128×16 Decode Tiles)

AIE micro-tile sweep · +23% NPU decode (1.14 → 1.40 t/s) · SRAM budget analysis · instruction count as dominant factor · 2026-03-30

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11

Phase 11 — Dispatch Reduction Investigation (Compute-Bound)

xrt::runlist · TILE_M=4096/14336 xclbins · bo_b dedup · 0.6% AIE utilisation discovered · 2026-03-30

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10

Phase 10 — Weight Tile Pre-staging (bo_a Cache)

bo_a DMA eliminated · +3% prefill · 112 MB saved · audit fixes · 2026-03-29

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9

Phase 9 — Root Cause Investigation & Phase 6 Restoration

Phase 7 decode misattribution corrected · NPU prefill restored (12–18 t/s) · dispatch timing removed · 2026-03-28

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8

Phase 8 — Vulkan Decode Ceiling Investigation

Batch sweep · int4 · cascade · speculative decoding · 43.7 t/s Vulkan ceiling confirmed · 2026-03-26

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7

Phase 7 — Vulkan Prefill (930 t/s) ⚠️ Decode Claim Corrected

930 t/s Vulkan prefill ✓ · 43.84 t/s decode was Vulkan, not NPU · see Phase 9 · 2026-03-26

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6

Phase 6 — Multi-Core NPU (4-Column, TILE_N=256)

pp2048: 19.5 t/s (+51% vs Phase 5) · all 4 K-slots on 4-col xclbins

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5

Phase 5 — Long Context & 1-Column NPU

8k context validated · NPU 2–3× over CPU · attention fallback characterised

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4

Phase 4 — Power Measurement & Workload Isolation

NPU on dedicated XDNA2 silicon · bench-power.sh · J/tok baseline

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3

Phase 3 — 8B Model Support (4 K-Slots)

K=4096 and K=14336 · Llama 3.1 8B fully covered · tile-loop optimisation

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2

Phase 2 — Dual-Slot Dispatch

K=5632 FFN layers on NPU · multi-slot architecture (up to 8 slots)

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1

Phase 1 — NPU Baseline

First working XDNA2 backend · weight cache · K=2048 · TinyLlama 1.1B

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